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author | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
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committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
commit | 031f396c71e750fede19651ba3a14e262a87e117 (patch) | |
tree | bfd6520d87f36775200aff930b632bfe3c80af1e /src/arch/arm/insts/macromem.hh | |
parent | e65f480d62e0112e89af6130e2f2024d89417df0 (diff) | |
download | gem5-031f396c71e750fede19651ba3a14e262a87e117.tar.xz |
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:
URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.
Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
Diffstat (limited to 'src/arch/arm/insts/macromem.hh')
-rw-r--r-- | src/arch/arm/insts/macromem.hh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 1a2db8b9a..4933a1e7c 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp { } }; + +/** + * Microops of the form + * PC = IntRegA + * CPSR = IntRegB + */ +class MicroSetPCCPSR : public MicroOp +{ + protected: + IntRegIndex ura, urb, urc; + + MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, + IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) + : MicroOp(mnem, machInst, __opClass), + ura(_ura), urb(_urb), urc(_urc) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + /** * Microops of the form IntRegA = IntRegB */ |