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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 4eb18cc07acdd3cbb64770d04c8ed7da50fae146 (patch) | |
| tree | a7e2cdc35cf634a85ea5d9dd6f2bab4273af762d /src/arch/arm/insts/mem.cc | |
| parent | 2fb8d481ab37db60a27126d151be23fad10adc50 (diff) | |
| download | gem5-4eb18cc07acdd3cbb64770d04c8ed7da50fae146.tar.xz | |
ARM: Improve memory instruction disassembly.
Diffstat (limited to 'src/arch/arm/insts/mem.cc')
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 7909330aa..afbf05e44 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -37,14 +37,17 @@ Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - return ss.str(); -} - -std::string -MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const -{ - std::stringstream ss; - printMnemonic(ss); + printReg(ss, machInst.rd); + ss << ", ["; + printReg(ss, machInst.rn); + ss << ", "; + if (machInst.puswl.prepost == 1) + printOffset(ss); + ss << "]"; + if (machInst.puswl.prepost == 0) + printOffset(ss); + else if (machInst.puswl.writeback) + ss << "!"; return ss.str(); } } |