diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/arm/insts/mem.cc | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/arm/insts/mem.cc')
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 558235340..3b57aae64 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -54,7 +54,7 @@ MemoryReg::printOffset(std::ostream &os) const { if (!add) os << "-"; - printReg(os, index); + printIntReg(os, index); if (shiftType != LSL || shiftAmt != 0) { switch (shiftType) { case LSL: @@ -82,11 +82,11 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const { stringstream ss; printMnemonic(ss); - printReg(ss, dest); + printIntReg(ss, dest); ss << ", "; - printReg(ss, op1); + printIntReg(ss, op1); ss << ", ["; - printReg(ss, base); + printIntReg(ss, base); ss << "]"; return ss.str(); } @@ -109,7 +109,7 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printMnemonic(ss, "ib"); break; } - printReg(ss, base); + printIntReg(ss, base); if (wb) { ss << "!"; } @@ -134,7 +134,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printMnemonic(ss, "ib"); break; } - printReg(ss, INTREG_SP); + printIntReg(ss, INTREG_SP); if (wb) { ss << "!"; } @@ -180,7 +180,7 @@ Memory::printInst(std::ostream &os, AddrMode addrMode) const printMnemonic(os); printDest(os); os << ", ["; - printReg(os, base); + printIntReg(os, base); if (addrMode != AddrMd_PostIndex) { os << ", "; printOffset(os); |