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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | ec4cd00b1101d7436ff2019dfc9fc1c09442c9c9 (patch) | |
| tree | 9bf1a2f687e2103d6f099a0e421a641717b3b45a /src/arch/arm/insts/mem.cc | |
| parent | 1ada9d48802ad2bccb1c1d9269797778198038fd (diff) | |
| download | gem5-ec4cd00b1101d7436ff2019dfc9fc1c09442c9c9.tar.xz | |
ARM: Add a base class for the RFE instruction.
Diffstat (limited to 'src/arch/arm/insts/mem.cc')
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 521499847..394c159d1 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -62,6 +62,31 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } +string +RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + stringstream ss; + switch (mode) { + case DecrementAfter: + printMnemonic(ss, "da"); + break; + case DecrementBefore: + printMnemonic(ss, "db"); + break; + case IncrementAfter: + printMnemonic(ss, "ia"); + break; + case IncrementBefore: + printMnemonic(ss, "ib"); + break; + } + printReg(ss, base); + if (wb) { + ss << "!"; + } + return ss.str(); +} + void Memory::printInst(std::ostream &os, AddrMode addrMode) const { |