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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | dbee6e0c5406200066b8185fd38fa47dae7cdd2f (patch) | |
| tree | cc1cb169d8a215010d2adbf1b4eea82d70fa695a /src/arch/arm/insts/mem.cc | |
| parent | 239c9af90d61b2877a8cee8b91f162e7a0bf1e72 (diff) | |
| download | gem5-dbee6e0c5406200066b8185fd38fa47dae7cdd2f.tar.xz | |
ARM: Add a base class for SRS.
Diffstat (limited to 'src/arch/arm/insts/mem.cc')
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 394c159d1..eb16e42d0 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -87,6 +87,61 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } +string +SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + stringstream ss; + switch (mode) { + case DecrementAfter: + printMnemonic(ss, "da"); + break; + case DecrementBefore: + printMnemonic(ss, "db"); + break; + case IncrementAfter: + printMnemonic(ss, "ia"); + break; + case IncrementBefore: + printMnemonic(ss, "ib"); + break; + } + printReg(ss, INTREG_SP); + if (wb) { + ss << "!"; + } + ss << ", #"; + switch (mode) { + case MODE_USER: + ss << "user"; + break; + case MODE_FIQ: + ss << "fiq"; + break; + case MODE_IRQ: + ss << "irq"; + break; + case MODE_SVC: + ss << "supervisor"; + break; + case MODE_MON: + ss << "monitor"; + break; + case MODE_ABORT: + ss << "abort"; + break; + case MODE_UNDEFINED: + ss << "undefined"; + break; + case MODE_SYSTEM: + ss << "system"; + break; + default: + ss << "unrecognized"; + break; + } + return ss.str(); +} + void Memory::printInst(std::ostream &os, AddrMode addrMode) const { |