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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | bb6fea91da7c5436d26d6b93f22b2dd5cd6287ba (patch) | |
| tree | 60685658c676826c90f3938c589880ef892a6b97 /src/arch/arm/insts/mem.cc | |
| parent | dbee6e0c5406200066b8185fd38fa47dae7cdd2f (diff) | |
| download | gem5-bb6fea91da7c5436d26d6b93f22b2dd5cd6287ba.tar.xz | |
ARM: Implement the SRS instruction.
Diffstat (limited to 'src/arch/arm/insts/mem.cc')
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index eb16e42d0..ccac3a25d 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -110,7 +110,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << "!"; } ss << ", #"; - switch (mode) { + switch (regMode) { case MODE_USER: ss << "user"; break; |