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authorMatt Horsnell <Matt.Horsnell@arm.com>2011-03-17 19:20:19 -0500
committerMatt Horsnell <Matt.Horsnell@arm.com>2011-03-17 19:20:19 -0500
commit031f396c71e750fede19651ba3a14e262a87e117 (patch)
treebfd6520d87f36775200aff930b632bfe3c80af1e /src/arch/arm/insts/mem.hh
parente65f480d62e0112e89af6130e2f2024d89417df0 (diff)
downloadgem5-031f396c71e750fede19651ba3a14e262a87e117.tar.xz
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
Diffstat (limited to 'src/arch/arm/insts/mem.hh')
-rw-r--r--src/arch/arm/insts/mem.hh8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index a4fc62603..324d86fed 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -97,14 +97,18 @@ class RfeOp : public MightBeMicro
IntRegIndex base;
AddrMode mode;
bool wb;
- static const unsigned numMicroops = 2;
+ IntRegIndex ura, urb, urc;
+ static const unsigned numMicroops = 3;
StaticInstPtr *uops;
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _base, AddrMode _mode, bool _wb)
: MightBeMicro(mnem, _machInst, __opClass),
- base(_base), mode(_mode), wb(_wb), uops(NULL)
+ base(_base), mode(_mode), wb(_wb),
+ ura(INTREG_UREG0), urb(INTREG_UREG1),
+ urc(INTREG_UREG2),
+ uops(NULL)
{}
virtual