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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
commitec4cd00b1101d7436ff2019dfc9fc1c09442c9c9 (patch)
tree9bf1a2f687e2103d6f099a0e421a641717b3b45a /src/arch/arm/insts/mem.hh
parent1ada9d48802ad2bccb1c1d9269797778198038fd (diff)
downloadgem5-ec4cd00b1101d7436ff2019dfc9fc1c09442c9c9.tar.xz
ARM: Add a base class for the RFE instruction.
Diffstat (limited to 'src/arch/arm/insts/mem.hh')
-rw-r--r--src/arch/arm/insts/mem.hh24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index dc4b7d627..d5b5d3519 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -63,6 +63,30 @@ class Swap : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+// The address is a base register plus an immediate.
+class RfeOp : public PredOp
+{
+ public:
+ enum AddrMode {
+ DecrementAfter,
+ DecrementBefore,
+ IncrementAfter,
+ IncrementBefore
+ };
+ protected:
+ IntRegIndex base;
+ AddrMode mode;
+ bool wb;
+
+ RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _base, AddrMode _mode, bool _wb)
+ : PredOp(mnem, _machInst, __opClass),
+ base(_base), mode(_mode), wb(_wb)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class Memory : public PredOp
{
public: