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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | b1158e493843066acdba153c89573273f5d0fd73 (patch) | |
| tree | 1ec9ac7d5355ec1ed6a3335cad8996449fb39e82 /src/arch/arm/insts/misc.cc | |
| parent | 504ac6518bea90d614c2d2394fa3881f8557d798 (diff) | |
| download | gem5-b1158e493843066acdba153c89573273f5d0fd73.tar.xz | |
ARM: Add a register, immediate, immediate to register base for [su]bfx.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 3ad49bb9d..20f102e72 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -197,6 +197,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ccprintf(ss, ", #%d, #%d", imm1, imm2); + return ss.str(); +} + +std::string RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |