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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:10 +0000 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
commit | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (patch) | |
tree | 9ea079dc4bc5b04cfc4b84a32c06225670be69dd /src/arch/arm/insts/misc.cc | |
parent | b9edb351454c2601070fb9432f23fc3914eb33c1 (diff) | |
download | gem5-eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05.tar.xz |
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
-rw-r--r-- | src/arch/arm/insts/misc.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index ec1b9358c..ba97eff09 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013 ARM Limited + * Copyright (c) 2010, 2012-2013, 2017 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -322,6 +322,16 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +MiscRegRegImmMemOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printIntReg(ss, op1); + return ss.str(); +} + +std::string UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", machInst); |