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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-25 11:14:47 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-22 09:17:22 +0000 |
commit | 12eac0c88e21ddc76593079127a4507558cddc40 (patch) | |
tree | 00cd013d61e15795421a8ea9d5cafe6c6c62ba33 /src/arch/arm/insts/misc.cc | |
parent | a0649ee1e90e6c71f74425457c381e8b6c5d0d43 (diff) | |
download | gem5-12eac0c88e21ddc76593079127a4507558cddc40.tar.xz |
arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers
from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match
with AArch64 implementation.
Change-Id: I27b0d65925d7965589b765269ae54129426e4c88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15735
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
-rw-r--r-- | src/arch/arm/insts/misc.cc | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index ef78c236e..3f2986525 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -326,3 +326,72 @@ UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); } + +McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, + uint64_t _iss, MiscRegIndex _miscReg) + : ArmStaticInst(_mnemonic, _machInst, No_OpClass) +{ + flags[IsNonSpeculative] = true; + iss = _iss; + miscReg = _miscReg; +} + +Fault +McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const +{ + uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); + uint32_t hcr = xc->readMiscReg(MISCREG_HCR); + uint32_t scr = xc->readMiscReg(MISCREG_SCR); + uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); + uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); + uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, + hcptr, iss); + if (hypTrap) { + return std::make_shared<HypervisorTrap>(machInst, iss, + EC_TRAPPED_CP15_MCR_MRC); + } else { + return NoFault; + } +} + +std::string +McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + return csprintf("%-10s (pipe flush)", mnemonic); +} + +McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic, + ExtMachInst _machInst, uint64_t _iss, + MiscRegIndex _miscReg) + : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg) +{} + +Fault +McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const +{ + uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); + uint32_t hcr = xc->readMiscReg(MISCREG_HCR); + uint32_t scr = xc->readMiscReg(MISCREG_SCR); + uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); + uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); + uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, + hcptr, iss); + if (hypTrap) { + return std::make_shared<HypervisorTrap>(machInst, iss, + EC_TRAPPED_CP15_MCR_MRC); + } else { + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); + } +} + +std::string +McrMrcImplDefined::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + return csprintf("%-10s (implementation defined)", mnemonic); +} |