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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | 498f9d925e0339389a19bb63d9508e6c780ba04b (patch) | |
| tree | 00a1726357e965be3a12208c6fcd59e646753bd6 /src/arch/arm/insts/misc.cc | |
| parent | f581fd3f899648f8699f53ecdc913e7d50c26f8f (diff) | |
| download | gem5-498f9d925e0339389a19bb63d9508e6c780ba04b.tar.xz | |
ARM: Add a base class for the sel instruction.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index c5430400d..b5ae61f5a 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -169,6 +169,19 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ss << ", "; + printReg(ss, op2); + return ss.str(); +} + +std::string RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |