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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | 554fb3774e638c9a6e7ce4b10a6da6d795a29206 (patch) | |
| tree | 4d4e5030537888a555d8ed682012db491f413a27 /src/arch/arm/insts/misc.cc | |
| parent | cb2e3b0acedbad6b35c0b2a56141399cf4d1c522 (diff) | |
| download | gem5-554fb3774e638c9a6e7ce4b10a6da6d795a29206.tar.xz | |
ARM: Add a base class for extend and add instructions.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index f8106c33a..c5430400d 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -155,6 +155,20 @@ RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ss << ", "; + printReg(ss, op2); + ccprintf(ss, ", #%d", imm); + return ss.str(); +} + +std::string RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |