arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

1 files changed, 42 insertions, 44 deletions

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 790989d9d..0114a4aba 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -47,21 +47,20 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
     bool foundPsr = false;
     for (unsigned i = 0; i < numSrcRegs(); i++) {
-        RegIndex idx = srcRegIdx(i);
-        RegIndex rel_idx;
-        if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
+        RegId reg = srcRegIdx(i);
+        if (reg.regClass != MiscRegClass) {
             continue;
         }
-        if (rel_idx == MISCREG_CPSR) {
+        if (reg.regIdx == MISCREG_CPSR) {
             ss << "cpsr";
             foundPsr = true;
             break;
         }
-        if (rel_idx == MISCREG_SPSR) {
+        if (reg.regIdx == MISCREG_SPSR) {
             ss << "spsr";
             foundPsr = true;
             break;
@@ -80,17 +79,16 @@ MsrBase::printMsrBase(std::ostream &os) const
     bool apsr = false;
     bool foundPsr = false;
     for (unsigned i = 0; i < numDestRegs(); i++) {
-        int idx = destRegIdx(i);
-        if (idx < Misc_Reg_Base) {
+        RegId reg = destRegIdx(i);
+        if (reg.regClass != MiscRegClass) {
             continue;
         }
-        idx -= Misc_Reg_Base;
-        if (idx == MISCREG_CPSR) {
+        if (reg.regIdx == MISCREG_CPSR) {
             os << "cpsr_";
             foundPsr = true;
             break;
         }
-        if (idx == MISCREG_SPSR) {
+        if (reg.regIdx == MISCREG_SPSR) {
             if (bits(byteMask, 1, 0)) {
                 os << "spsr_";
             } else {
@@ -142,7 +140,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     std::stringstream ss;
     printMsrBase(ss);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -151,11 +149,11 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, dest2);
+    printIntReg(ss, dest2);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -164,11 +162,11 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     return ss.str();
 }
 
@@ -186,7 +184,7 @@ RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -196,9 +194,9 @@ RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -207,11 +205,11 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -221,13 +219,13 @@ RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ss << ", ";
-    printReg(ss, op3);
+    printIntReg(ss, op3);
     return ss.str();
 }
 
@@ -236,11 +234,11 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     return ss.str();
 }
 
@@ -249,9 +247,9 @@ RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -261,9 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -273,9 +271,9 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -285,7 +283,7 @@ RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -295,9 +293,9 @@ RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -307,9 +305,9 @@ RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, ", imm);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -318,10 +316,10 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, ", imm);
     printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }