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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
| commit | 6976b4890a307a2d8584b4e512e3f6d728e59ad5 (patch) | |
| tree | 7da45cfa95788995d576793b49a9d7eb1c4c948e /src/arch/arm/insts/misc.cc | |
| parent | 186cfe3ae30970b43c09cccab6f004ea7d720838 (diff) | |
| download | gem5-6976b4890a307a2d8584b4e512e3f6d728e59ad5.tar.xz | |
ARM: Add a RegRegImmOp base class.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 87d3d1796..a5a4e3b32 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -206,6 +206,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ccprintf(ss, ", #%d", imm); + return ss.str(); +} + +std::string RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |