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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | c643b1c2749703b7823d665a7d89d0333f5c6e95 (patch) | |
| tree | cb9f0c6bbe54fae00f0803830bc9b2a04eea2bf3 /src/arch/arm/insts/misc.cc | |
| parent | 64ade8316ee563448d8c8f98a70cc4d9d0c66707 (diff) | |
| download | gem5-c643b1c2749703b7823d665a7d89d0333f5c6e95.tar.xz | |
ARM: Add a base class to support usada8.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index b5ae61f5a..3ad49bb9d 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -169,6 +169,21 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ss << ", "; + printReg(ss, op2); + ss << ", "; + printReg(ss, op3); + return ss.str(); +} + +std::string RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |