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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
| commit | c981a4de2b317a3e5dd6813e809973c7d6734f41 (patch) | |
| tree | 3f0b326d5957478f429980e8ffd8a002076b4037 /src/arch/arm/insts/misc.cc | |
| parent | 57443a2144c6f446c7b7a3de7389ae794d591330 (diff) | |
| download | gem5-c981a4de2b317a3e5dd6813e809973c7d6734f41.tar.xz | |
ARM: Add base classes suitable for the REV* instructions.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 588586e00..3547c6712 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -142,3 +142,14 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printReg(ss, op1); return ss.str(); } + +std::string +RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + return ss.str(); +} |