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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | e9c8f68c0fcfb72934b852a61671fb94a1927e1d (patch) | |
| tree | 25c89e490c733f3a3afdd775f2c7a094a69fe4a1 /src/arch/arm/insts/misc.cc | |
| parent | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (diff) | |
| download | gem5-e9c8f68c0fcfb72934b852a61671fb94a1927e1d.tar.xz | |
ARM: Make undefined instructions obey predication.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 0eae37de0..a0af4fc2f 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -261,3 +261,11 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printReg(ss, op1); return ss.str(); } + +std::string +UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", + "unknown", machInst, machInst.opcode, + inst2string(machInst)); +} |