ARM: Define versions of MSR and MRS outside the decoder.

1 files changed, 144 insertions, 0 deletions

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
new file mode 100644
index 000000000..588586e00
--- /dev/null
+++ b/src/arch/arm/insts/misc.cc
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/arm/insts/misc.hh"
+
+std::string
+MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ss << ", ";
+    bool foundPsr = false;
+    for (unsigned i = 0; i < numSrcRegs(); i++) {
+        int idx = srcRegIdx(i);
+        if (idx < Ctrl_Base_DepTag) {
+            continue;
+        }
+        idx -= Ctrl_Base_DepTag;
+        if (idx == MISCREG_CPSR) {
+            ss << "cpsr";
+            foundPsr = true;
+            break;
+        }
+        if (idx == MISCREG_SPSR) {
+            ss << "spsr";
+            foundPsr = true;
+            break;
+        }
+    }
+    if (!foundPsr) {
+        ss << "????";
+    }
+    return ss.str();
+}
+
+void
+MsrBase::printMsrBase(std::ostream &os) const
+{
+    printMnemonic(os);
+    bool apsr = false;
+    bool foundPsr = false;
+    for (unsigned i = 0; i < numDestRegs(); i++) {
+        int idx = destRegIdx(i);
+        if (idx < Ctrl_Base_DepTag) {
+            continue;
+        }
+        idx -= Ctrl_Base_DepTag;
+        if (idx == MISCREG_CPSR) {
+            os << "cpsr_";
+            foundPsr = true;
+            break;
+        }
+        if (idx == MISCREG_SPSR) {
+            if (bits(byteMask, 1, 0)) {
+                os << "spsr_";
+            } else {
+                os << "apsr_";
+                apsr = true;
+            }
+            foundPsr = true;
+            break;
+        }
+    }
+    if (!foundPsr) {
+        os << "????";
+        return;
+    }
+    if (bits(byteMask, 3)) {
+        if (apsr) {
+            os << "nzcvq";
+        } else {
+            os << "f";
+        }
+    }
+    if (bits(byteMask, 2)) {
+        if (apsr) {
+            os << "g";
+        } else {
+            os << "s";
+        }
+    }
+    if (bits(byteMask, 1)) {
+        os << "x";
+    }
+    if (bits(byteMask, 0)) {
+        os << "c";
+    }
+}
+
+std::string
+MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMsrBase(ss);
+    ccprintf(ss, ", #%#x", imm);
+    return ss.str();
+}
+
+std::string
+MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMsrBase(ss);
+    ss << ", ";
+    printReg(ss, op1);
+    return ss.str();
+}