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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
| commit | 7aa423acad07f05ee547117406a72a5c1b4f6015 (patch) | |
| tree | a4a9f24bb94a743b0316ea2a907d07daddc4ffc3 /src/arch/arm/insts/misc.cc | |
| parent | 4f5775df64b1b16ef4a3a02b12e4ac8a6370baed (diff) | |
| download | gem5-7aa423acad07f05ee547117406a72a5c1b4f6015.tar.xz | |
cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.
Diffstat (limited to 'src/arch/arm/insts/misc.cc')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 7d383a87a..c40b6711f 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -38,6 +39,7 @@ */ #include "arch/arm/insts/misc.hh" +#include "cpu/reg_class.hh" std::string MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const @@ -48,17 +50,17 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << ", "; bool foundPsr = false; for (unsigned i = 0; i < numSrcRegs(); i++) { - int idx = srcRegIdx(i); - if (idx < Ctrl_Base_DepTag) { + RegIndex idx = srcRegIdx(i); + RegIndex rel_idx; + if (regIdxToClass(idx, &rel_idx) != MiscRegClass) { continue; } - idx -= Ctrl_Base_DepTag; - if (idx == MISCREG_CPSR) { + if (rel_idx == MISCREG_CPSR) { ss << "cpsr"; foundPsr = true; break; } - if (idx == MISCREG_SPSR) { + if (rel_idx == MISCREG_SPSR) { ss << "spsr"; foundPsr = true; break; |