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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | fb2329791464a3ea9d8c13a6aa17bf9e379dbdb9 (patch) | |
| tree | b56d402a901c20554f545d4a4a6186390dd77c28 /src/arch/arm/insts/misc.hh | |
| parent | 247acd93c49be2d9a677775e8684f6971b6c5364 (diff) | |
| download | gem5-fb2329791464a3ea9d8c13a6aa17bf9e379dbdb9.tar.xz | |
ARM: Make a base class for instructions that use only an immediate.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 23f777c2d..8080c4e1f 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -94,6 +94,19 @@ class MsrRegOp : public MsrBase std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class ImmOp : public PredOp +{ + protected: + uint32_t imm; + + ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + uint32_t _imm) : + PredOp(mnem, _machInst, __opClass), imm(_imm) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class RegRegOp : public PredOp { protected: |