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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-27 09:08:37 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-27 09:08:37 -0400
commitec41000dadd5256fd90f0bfdc97264946e50a3aa (patch)
treeb045e00e601839d4f49cb85321b544b71341abce /src/arch/arm/insts/misc.hh
parent341dbf266258dcbdb1e5e9f09c244b8ac271faaf (diff)
downloadgem5-ec41000dadd5256fd90f0bfdc97264946e50a3aa.tar.xz
arm: Fixed undefined behaviours identified by gcc
This patch fixes the runtime errors highlighted by the undefined behaviour sanitizer. In the end there were two issues. First, when rotating an immediate, we ended up shifting an uint32_t by 32 in some cases. This case is fixed by checking for a rotation by 0 positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex as an IntRegIndex. This issue is resolved by introducing a MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types. With these fixes there are no runtime errors identified for the full ARM regressions.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
-rw-r--r--src/arch/arm/insts/misc.hh34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 3d947a272..4217dc6f1 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -256,6 +256,40 @@ class RegRegImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class MiscRegRegImmOp : public PredOp
+{
+ protected:
+ MiscRegIndex dest;
+ IntRegIndex op1;
+ uint64_t imm;
+
+ MiscRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ MiscRegIndex _dest, IntRegIndex _op1,
+ uint64_t _imm) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class RegMiscRegImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ MiscRegIndex op1;
+ uint64_t imm;
+
+ RegMiscRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, MiscRegIndex _op1,
+ uint64_t _imm) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegImmImmOp : public PredOp
{
protected: