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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-10 15:35:26 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-21 14:25:56 +0000 |
| commit | 2a2c66c16c659af4c3588b6c1646d55c66ad53fe (patch) | |
| tree | 633dd84e28b040febbe2fd2efc7cd0a62dc7f60d /src/arch/arm/insts/misc64.cc | |
| parent | d3ec34201c14d551e864372a89ccddb1c255e77a (diff) | |
| download | gem5-2a2c66c16c659af4c3588b6c1646d55c66ad53fe.tar.xz | |
arch-arm: Fix MSR/MRS disassemble
This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name
Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/misc64.cc')
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 465bafa9e..b40de0229 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 ARM Limited + * Copyright (c) 2011-2013,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -53,7 +53,7 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string RegRegRegImmOp64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -71,3 +71,27 @@ UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", machInst); } + +std::string +MiscRegRegImmOp64::generateDisassembly( + Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printMiscReg(ss, dest); + ss << ", "; + printIntReg(ss, op1); + return ss.str(); +} + +std::string +RegMiscRegImmOp64::generateDisassembly( + Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printIntReg(ss, dest); + ss << ", "; + printMiscReg(ss, op1); + return ss.str(); +} |