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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-14 17:45:38 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:30:02 +0000 |
| commit | 803a8db53aae57d42bd2465c9284df91ed5e7641 (patch) | |
| tree | ffbc793bf70c643e6f1f686eb5cd8188737000c5 /src/arch/arm/insts/misc64.cc | |
| parent | a3bb33b257324ad9da3e656e30ba61e6f4b5497f (diff) | |
| download | gem5-803a8db53aae57d42bd2465c9284df91ed5e7641.tar.xz | |
arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly
This patch fixes the disassembly of AArch64 Exception Generating
instructions, which were not printing the encoded immediate field. This
has been accomplished by changing their underlying type to a newly
defined one.
Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8368
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/misc64.cc')
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index b40de0229..edc916dbb 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013,2017 ARM Limited + * Copyright (c) 2011-2013,2017-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -40,6 +40,15 @@ #include "arch/arm/insts/misc64.hh" std::string +ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + ccprintf(ss, "#0x%x", imm); + return ss.str(); +} + +std::string RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |