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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-24 16:21:41 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-26 09:45:47 +0000 |
commit | f5c8fc6bbedfe62bcb9514568b8ee13e073c807b (patch) | |
tree | 3a140bbf83c79635c15c20c29ed8673dfd978601 /src/arch/arm/insts/misc64.cc | |
parent | 68bc5397c937c7289ad7e78416132dc77ccf34a9 (diff) | |
download | gem5-f5c8fc6bbedfe62bcb9514568b8ee13e073c807b.tar.xz |
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.
Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/misc64.cc')
-rw-r--r-- | src/arch/arm/insts/misc64.cc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index b2761e76c..7df2f76ed 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -266,6 +266,8 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, assert(miscRead); trap_to_hyp = hcr.tid1 && el == EL1; break; + case MISCREG_IMPDEF_UNIMPL: + trap_to_hyp = hcr.tidcp && el == EL1; default: break; } @@ -330,3 +332,33 @@ RegMiscRegImmOp64::generateDisassembly( printMiscReg(ss, op1); return ss.str(); } + +Fault +MiscRegImplDefined64::execute(ExecContext *xc, + Trace::InstRecord *traceData) const +{ + auto tc = xc->tcBase(); + const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); + const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; + + Fault fault = trap(tc, miscReg, el, imm); + + if (fault != NoFault) { + return fault; + + } else if (warning) { + warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str()); + return NoFault; + + } else { + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); + } +} + +std::string +MiscRegImplDefined64::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + return csprintf("%-10s (implementation defined)", fullMnemonic.c_str()); +} |