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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-12 13:09:18 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-23 08:32:25 +0000 |
| commit | 32a23114c14cebc5ec0067ac739144b50e412219 (patch) | |
| tree | 1bc7685956be9cd1b6530c5a07a8232573e9992b /src/arch/arm/insts/misc64.cc | |
| parent | e9c7c8168081e38d272e7c83e7f9503b7e8f162f (diff) | |
| download | gem5-32a23114c14cebc5ec0067ac739144b50e412219.tar.xz | |
arch-arm: Trap virtual accesses to GICv3 SGI registers
According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.
Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/insts/misc64.cc')
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index c219bd9ad..fed2d9ac8 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013,2017-2018 ARM Limited + * Copyright (c) 2011-2013,2017-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -38,6 +38,7 @@ */ #include "arch/arm/insts/misc64.hh" +#include "arch/arm/isa.hh" std::string ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const @@ -268,6 +269,16 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, break; case MISCREG_IMPDEF_UNIMPL: trap_to_hyp = hcr.tidcp && el == EL1; + // GICv3 regs + case MISCREG_ICC_SGI0R_EL1: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trap_to_hyp = hcr.fmo && el == EL1; + break; + case MISCREG_ICC_SGI1R_EL1: + case MISCREG_ICC_ASGI1R_EL1: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trap_to_hyp = hcr.imo && el == EL1; + break; default: break; } |