arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.

Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 8af488a02..f70344bcb 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -178,4 +178,32 @@ class RegMiscRegImmOp64 : public MiscRegOp64
             Addr pc, const SymbolTable *symtab) const override;
 };
 
+class MiscRegImplDefined64 : public MiscRegOp64
+{
+  protected:
+    const std::string fullMnemonic;
+    const MiscRegIndex miscReg;
+    const uint32_t imm;
+    const bool warning;
+
+  public:
+    MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
+                         MiscRegIndex misc_reg, bool misc_read,
+                         uint32_t _imm, const std::string full_mnem,
+                         bool _warning) :
+        MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
+        fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
+        warning(_warning)
+    {
+        assert(miscReg == MISCREG_IMPDEF_UNIMPL);
+    }
+
+  protected:
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+};
+
 #endif