arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 35 insertions, 1 deletions

diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e18224..384d94628 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@ class UnknownOp64 : public ArmStaticInst
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+    MiscRegIndex dest;
+    IntRegIndex op1;
+    uint32_t imm;
+
+    MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+                      OpClass __opClass, MiscRegIndex _dest,
+                      IntRegIndex _op1, uint32_t _imm) :
+        ArmStaticInst(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    MiscRegIndex op1;
+    uint32_t imm;
+
+    RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+                      OpClass __opClass, IntRegIndex _dest,
+                      MiscRegIndex _op1, uint32_t _imm) :
+        ArmStaticInst(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 #endif