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authorARM gem5 Developers <none@none>2014-01-24 15:29:34 -0600
committerARM gem5 Developers <none@none>2014-01-24 15:29:34 -0600
commit612f8f074fa1099cf70faf495d46cc647762a031 (patch)
treebd1e99c43bf15292395eadd4b7ae3f5c823545c3 /src/arch/arm/insts/pred_inst.hh
parentf3585c841e964c98911784a187fc4f081a02a0a6 (diff)
downloadgem5-612f8f074fa1099cf70faf495d46cc647762a031.tar.xz
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
Diffstat (limited to 'src/arch/arm/insts/pred_inst.hh')
-rw-r--r--src/arch/arm/insts/pred_inst.hh36
1 files changed, 24 insertions, 12 deletions
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index c441d1f32..c5e2ab386 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -78,7 +78,8 @@ modified_imm(uint8_t ctrlImm, uint8_t dataImm)
}
static inline uint64_t
-simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid)
+simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
+ bool isAarch64 = false)
{
uint64_t bigData = data;
immValid = true;
@@ -133,12 +134,20 @@ simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid)
}
break;
case 0xf:
- if (!op) {
- uint64_t bVal = bits(bigData, 6) ? (0x1F) : (0x20);
- bigData = (bits(bigData, 5, 0) << 19) |
- (bVal << 25) | (bits(bigData, 7) << 31);
- bigData |= (bigData << 32);
- break;
+ {
+ uint64_t bVal = 0;
+ if (!op) {
+ bVal = bits(bigData, 6) ? (0x1F) : (0x20);
+ bigData = (bits(bigData, 5, 0) << 19) |
+ (bVal << 25) | (bits(bigData, 7) << 31);
+ bigData |= (bigData << 32);
+ break;
+ } else if (isAarch64) {
+ bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
+ bigData = (bits(bigData, 5, 0) << 48) |
+ (bVal << 54) | (bits(bigData, 7) << 63);
+ break;
+ }
}
// Fall through, immediate encoding is invalid.
default:
@@ -179,11 +188,14 @@ class PredOp : public ArmStaticInst
/// Constructor
PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- ArmStaticInst(mnem, _machInst, __opClass),
- condCode(machInst.itstateMask ?
- (ConditionCode)(uint8_t)machInst.itstateCond :
- (ConditionCode)(unsigned)machInst.condCode)
+ ArmStaticInst(mnem, _machInst, __opClass)
{
+ if (machInst.aarch64)
+ condCode = COND_UC;
+ else if (machInst.itstateMask)
+ condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
+ else
+ condCode = (ConditionCode)(unsigned)machInst.condCode;
}
};