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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-24 16:11:38 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:32:53 +0000 |
| commit | 80427ea030b521779521f57b092bc6b4afc86ab2 (patch) | |
| tree | 257b857eda172dde3fe86d19b1d23bffffed256e /src/arch/arm/insts/pseudo.cc | |
| parent | 8e17f07c295cec854d89cbf427bbd2f8dd915eda (diff) | |
| download | gem5-80427ea030b521779521f57b092bc6b4afc86ab2.tar.xz | |
arch-arm: IMPLEMENTATION DEFINED register
A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.
Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/pseudo.cc')
| -rw-r--r-- | src/arch/arm/insts/pseudo.cc | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc index 40e00accf..e2504d61e 100644 --- a/src/arch/arm/insts/pseudo.cc +++ b/src/arch/arm/insts/pseudo.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014,2016-2017 ARM Limited + * Copyright (c) 2014,2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -181,10 +181,8 @@ WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); } - - McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, - uint64_t _iss, MiscRegIndex _miscReg) + uint64_t _iss, MiscRegIndex _miscReg) : ArmStaticInst(_mnemonic, _machInst, No_OpClass) { flags[IsNonSpeculative] = true; @@ -217,3 +215,37 @@ McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s (pipe flush)", mnemonic); } + +McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic, + ExtMachInst _machInst, uint64_t _iss, + MiscRegIndex _miscReg) + : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg) +{} + +Fault +McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const +{ + uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); + uint32_t hcr = xc->readMiscReg(MISCREG_HCR); + uint32_t scr = xc->readMiscReg(MISCREG_SCR); + uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); + uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); + uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, + hcptr, iss); + if (hypTrap) { + return std::make_shared<HypervisorTrap>(machInst, iss, + EC_TRAPPED_CP15_MCR_MRC); + } else { + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); + } +} + +std::string +McrMrcImplDefined::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + return csprintf("%-10s (implementation defined)", mnemonic); +} |