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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-01-24 15:53:43 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-16 09:32:53 +0000
commit8e17f07c295cec854d89cbf427bbd2f8dd915eda (patch)
tree474b9791cdbb5920fa3b3ceff107b82d9a62184c /src/arch/arm/insts/pseudo.hh
parent94553f32d8dbb7979dbeb0e6bafaa5db1985db1e (diff)
downloadgem5-8e17f07c295cec854d89cbf427bbd2f8dd915eda.tar.xz
arch-arm: Arch regs and pseudo regs distinction
A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used as a boundary for the number of physical (real) Misc registers in the system. Pseudo registers (like CP15_UNIMPL) have been moved after the NUM_PHYS_MISCREGS identifier, so that their enum number is (NUM_PHYS_MISCREGS < number < NUM_MISCREGS). Moving away those registers has created some free slots that can be used for future Misc register implementation. SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers. This allows us to define as many pseudo registers as we want without being concerned about checkpoint compatibility. Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7921 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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