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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-09 10:10:04 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-07 15:13:49 +0000 |
| commit | 7798ffb6948d12c7f2bc63dc9a3263bb19aa3297 (patch) | |
| tree | 24e2a42dc06b980a86e7763b6b01d9fd7aa372e0 /src/arch/arm/insts/static_inst.cc | |
| parent | 633fdd5841d8e7798e1b1158261612a6ad84c812 (diff) | |
| download | gem5-7798ffb6948d12c7f2bc63dc9a3263bb19aa3297.tar.xz | |
arch-arm: Change function name for banked miscregs
This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.
Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/static_inst.cc')
| -rw-r--r-- | src/arch/arm/insts/static_inst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index f7a9745ad..aace1de2b 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -880,7 +880,7 @@ ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const // Get the index of the banked version of SCTLR: // SCTLR_s or SCTLR_ns. - auto banked_sctlr = flattenMiscRegNsBanked( + auto banked_sctlr = snsBankedIndex( MISCREG_SCTLR, tc, !inSecureState(tc)); // SCTLR.SED bit is enabling/disabling the ue of SETEND instruction. |