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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/arch/arm/insts/static_inst.cc | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/arch/arm/insts/static_inst.cc')
| -rw-r--r-- | src/arch/arm/insts/static_inst.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 417496579..9f878ac4d 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -337,8 +337,6 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const case CCRegClass: ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]); break; - case VectorRegClass: - panic("ARM ISA does not have any vector registers yet!"); } } |