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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
commit | f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa (patch) | |
tree | d08e72f1eeeea81b33b60b6bd0f90f1cbd9f174d /src/arch/arm/insts/static_inst.hh | |
parent | 53ae19bb5dce904915385515d87ff3c9a69ee170 (diff) | |
download | gem5-f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa.tar.xz |
arm: Correctly check FP/SIMD access permission in aarch32
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.
Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Diffstat (limited to 'src/arch/arm/insts/static_inst.hh')
-rw-r--r-- | src/arch/arm/insts/static_inst.hh | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index d4684c78f..9ca64d1fe 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013 ARM Limited + * Copyright (c) 2010-2013, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -363,6 +363,47 @@ class ArmStaticInst : public StaticInst mnemonic, true); } + /** + * Trap an access to Advanced SIMD or FP registers due to access + * control bits. + * + * See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the + * ARM ARM psueodcode library. + * + * @param el Target EL for the trap + */ + Fault advSIMDFPAccessTrap64(ExceptionLevel el) const; + + + /** + * Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. + * + * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the + * ARM ARM psueodcode library. + */ + Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const; + + /** + * Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and + * CPTR_EL3. + * + * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the + * ARM ARM psueodcode library. + */ + Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, + CPSR cpsr, CPACR cpacr) const; + + /** + * Check if a VFP/SIMD access from aarch32 should be allowed. + * + * See aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled in the + * ARM ARM psueodcode library. + */ + Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, + CPSR cpsr, CPACR cpacr, + NSACR nsacr, FPEXC fpexc, + bool fpexc_check, bool advsimd) const; + public: virtual void annotateFault(ArmFault *fault) {} |