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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-01 15:33:06 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-13 09:24:57 +0000 |
| commit | 2bc7810cfc4feba7bd320cc65c78a3351dff5e3f (patch) | |
| tree | cf750929da236adf577fc6d98304d6fc4c850159 /src/arch/arm/insts/static_inst.hh | |
| parent | 0a67a7a7ce42fd1af0f5013b9723126e18f45378 (diff) | |
| download | gem5-2bc7810cfc4feba7bd320cc65c78a3351dff5e3f.tar.xz | |
arch-arm: Corrected encoding for T32 HVC instruction
This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/insts/static_inst.hh')
0 files changed, 0 insertions, 0 deletions