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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:02 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:02 -0500
commit7939b4826506bde98d299e1ba7a38e17cd1fa785 (patch)
tree795354a368ad0d00a88e5d6a75c79e9a8daaa417 /src/arch/arm/insts/static_inst.hh
parentb66e3aec43a4adc85fb057db350c8984acf0bc40 (diff)
downloadgem5-7939b4826506bde98d299e1ba7a38e17cd1fa785.tar.xz
ARM: Implement disassembly for the new data processing classes.
Diffstat (limited to 'src/arch/arm/insts/static_inst.hh')
-rw-r--r--src/arch/arm/insts/static_inst.hh8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 99fa819b5..81b480e02 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -82,10 +82,16 @@ class ArmStaticInstBase : public StaticInst
void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
const std::string &prefix, const Addr addr,
const std::string &suffix) const;
- void printShiftOperand(std::ostream &os) const;
+ void printShiftOperand(std::ostream &os, IntRegIndex rm,
+ bool immShift, uint32_t shiftAmt,
+ IntRegIndex rs, ArmShiftType type) const;
void printDataInst(std::ostream &os, bool withImm) const;
+ void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
+ IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
+ IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
+ uint32_t imm) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;