arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

1 files changed, 23 insertions, 23 deletions

diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index c76f97ca6..f72fba675 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -51,9 +51,9 @@ FpCondCompRegOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", defCc);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
@@ -66,11 +66,11 @@ FpCondSelOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
     return ss.str();
@@ -81,9 +81,9 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     return ss.str();
 }
 
@@ -92,7 +92,7 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -102,9 +102,9 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -114,11 +114,11 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     return ss.str();
 }
 
@@ -129,11 +129,11 @@ FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
     std::stringstream ss;
     printMnemonic(ss);
     printCondition(ss, cond);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     return ss.str();
 }
 
@@ -142,13 +142,13 @@ FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     ss << ", ";
-    printReg(ss, op3 + FP_Reg_Base);
+    printFloatReg(ss, op3);
     return ss.str();
 }
 
@@ -157,11 +157,11 @@ FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }