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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:14 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:14 -0500
commitc1f7bf7f0e97f8470eb4280870244b6b673dbff4 (patch)
treec89128e4dff36de237bf7601936f6bb935621e00 /src/arch/arm/insts/vfp.hh
parentf245f4937b2f48df17795887bdde9aeaf4476e39 (diff)
downloadgem5-c1f7bf7f0e97f8470eb4280870244b6b673dbff4.tar.xz
ARM: Add support for VFP vector mode.
Diffstat (limited to 'src/arch/arm/insts/vfp.hh')
-rw-r--r--src/arch/arm/insts/vfp.hh65
1 files changed, 65 insertions, 0 deletions
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 8cffb276e..77e104a13 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -68,8 +68,73 @@ setVfpMicroFlags(VfpMicroMode mode, T &flags)
case VfpNotAMicroop:
break;
}
+ if (mode == VfpMicroop || mode == VfpFirstMicroop) {
+ flags[StaticInst::IsDelayedCommit] = true;
+ }
}
+class VfpMacroOp : public PredMacroOp
+{
+ public:
+ static bool
+ inScalarBank(IntRegIndex idx)
+ {
+ return (idx % 32) < 8;
+ }
+
+ protected:
+ bool wide;
+
+ VfpMacroOp(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, bool _wide) :
+ PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
+ {}
+
+ IntRegIndex
+ addStride(IntRegIndex idx, unsigned stride)
+ {
+ if (wide) {
+ stride *= 2;
+ }
+ unsigned offset = idx % 8;
+ idx = (IntRegIndex)(idx - offset);
+ offset += stride;
+ idx = (IntRegIndex)(idx + (offset % 8));
+ return idx;
+ }
+
+ void
+ nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
+ {
+ unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
+ assert(!inScalarBank(dest));
+ dest = addStride(dest, stride);
+ op1 = addStride(op1, stride);
+ if (!inScalarBank(op2)) {
+ op2 = addStride(op2, stride);
+ }
+ }
+
+ void
+ nextIdxs(IntRegIndex &dest, IntRegIndex &op1)
+ {
+ unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
+ assert(!inScalarBank(dest));
+ dest = addStride(dest, stride);
+ if (!inScalarBank(op1)) {
+ op1 = addStride(op1, stride);
+ }
+ }
+
+ void
+ nextIdxs(IntRegIndex &dest)
+ {
+ unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
+ assert(!inScalarBank(dest));
+ dest = addStride(dest, stride);
+ }
+};
+
class VfpRegRegOp : public RegRegOp
{
protected: