summaryrefslogtreecommitdiff
path: root/src/arch/arm/insts
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
commit70a75ceb84c3c1964db548a254e2b6abdf8c084c (patch)
tree42ffe6531449f4781962c1b13e9d7ab2e34ccf3f /src/arch/arm/insts
parent4eb18cc07acdd3cbb64770d04c8ed7da50fae146 (diff)
downloadgem5-70a75ceb84c3c1964db548a254e2b6abdf8c084c.tar.xz
ARM: Move the integer microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/macromem.hh17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 7b566bb57..c215cdeab 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -47,6 +47,23 @@ number_of_ones(int32_t val)
}
/**
+ * Microops of the form IntRegA = IntRegB op Imm
+ */
+class MicroIntOp : public PredOp
+{
+ protected:
+ RegIndex ura, urb;
+ uint8_t imm;
+
+ MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _ura, RegIndex _urb, uint8_t _imm)
+ : PredOp(mnem, machInst, __opClass),
+ ura(_ura), urb(_urb), imm(_imm)
+ {
+ }
+};
+
+/**
* Arm Macro Memory operations like LDM/STM
*/
class ArmMacroMemoryOp : public PredMacroOp