arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2 files changed, 269 insertions, 0 deletions

diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc
new file mode 100644
index 000000000..0f24d899b
--- /dev/null
+++ b/src/arch/arm/insts/sve_mem.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#include "arch/arm/insts/sve_mem.hh"
+
+namespace ArmISA
+{
+
+std::string
+SveMemVecFillSpill::generateDisassembly(Addr pc,
+                                        const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss, "", false);
+    printVecReg(ss, dest, true);
+    ccprintf(ss, ", [");
+    printIntReg(ss, base);
+    if (imm != 0) {
+        ccprintf(ss, ", #%d, mul vl", imm);
+    }
+    ccprintf(ss, "]");
+    return ss.str();
+}
+
+std::string
+SveMemPredFillSpill::generateDisassembly(Addr pc,
+                                         const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss, "", false);
+    printVecPredReg(ss, dest);
+    ccprintf(ss, ", [");
+    printIntReg(ss, base);
+    if (imm != 0) {
+        ccprintf(ss, ", #%d, mul vl", imm);
+    }
+    ccprintf(ss, "]");
+    return ss.str();
+}
+
+std::string
+SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    // TODO: add suffix to transfer register and scaling factor (LSL #<x>)
+    std::stringstream ss;
+    printMnemonic(ss, "", false);
+    ccprintf(ss, "{");
+    printVecReg(ss, dest, true);
+    ccprintf(ss, "}, ");
+    printVecPredReg(ss, gp);
+    ccprintf(ss, "/z, ");
+    ccprintf(ss, ", [");
+    printIntReg(ss, base);
+    ccprintf(ss, ", ");
+    printIntReg(ss, offset);
+    ccprintf(ss, "]");
+    return ss.str();
+}
+
+std::string
+SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    // TODO: add suffix to transfer register
+    std::stringstream ss;
+    printMnemonic(ss, "", false);
+    ccprintf(ss, "{");
+    printVecReg(ss, dest, true);
+    ccprintf(ss, "}, ");
+    printVecPredReg(ss, gp);
+    ccprintf(ss, "/z, ");
+    ccprintf(ss, ", [");
+    printIntReg(ss, base);
+    if (imm != 0) {
+        ccprintf(ss, ", #%d, mul vl", imm);
+    }
+    ccprintf(ss, "]");
+    return ss.str();
+}
+
+}  // namespace ArmISA
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
new file mode 100644
index 000000000..de6b69cd5
--- /dev/null
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#ifndef __ARCH_ARM_SVE_MEM_HH__
+#define __ARCH_ARM_SVE_MEM_HH__
+
+#include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/tlb.hh"
+
+namespace ArmISA
+{
+
+class SveMemVecFillSpill : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex base;
+    uint64_t imm;
+
+    /// True if the base register is SP (used for SP alignment checking).
+    bool baseIsSP;
+
+    unsigned memAccessFlags;
+
+    SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
+                       OpClass __opClass, IntRegIndex _dest,
+                       IntRegIndex _base, uint64_t _imm)
+        : ArmStaticInst(mnem, _machInst, __opClass),
+          dest(_dest), base(_base), imm(_imm),
+          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+    {
+        baseIsSP = isSP(_base);
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class SveMemPredFillSpill : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex base;
+    uint64_t imm;
+
+    /// True if the base register is SP (used for SP alignment checking).
+    bool baseIsSP;
+
+    unsigned memAccessFlags;
+
+    SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
+                        OpClass __opClass, IntRegIndex _dest,
+                        IntRegIndex _base, uint64_t _imm)
+        : ArmStaticInst(mnem, _machInst, __opClass),
+          dest(_dest), base(_base), imm(_imm),
+          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+    {
+        baseIsSP = isSP(_base);
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class SveContigMemSS : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex gp;
+    IntRegIndex base;
+    IntRegIndex offset;
+
+    /// True if the base register is SP (used for SP alignment checking).
+    bool baseIsSP;
+
+    unsigned memAccessFlags;
+
+    SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+                   IntRegIndex _offset)
+        : ArmStaticInst(mnem, _machInst, __opClass),
+          dest(_dest), gp(_gp), base(_base), offset(_offset),
+          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+    {
+        baseIsSP = isSP(_base);
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class SveContigMemSI : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex gp;
+    IntRegIndex base;
+    uint64_t imm;
+
+    /// True if the base register is SP (used for SP alignment checking).
+    bool baseIsSP;
+
+    unsigned memAccessFlags;
+
+    SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+                   uint64_t _imm)
+        : ArmStaticInst(mnem, _machInst, __opClass),
+          dest(_dest), gp(_gp), base(_base), imm(_imm),
+          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+    {
+        baseIsSP = isSP(_base);
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+}  // namespace ArmISA
+
+#endif  // __ARCH_ARM_SVE_MEM_HH__