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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-04-23 05:18:30 -0400
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-04-23 05:18:30 -0400
commitecf774bc561f139a13539d40dde075710f89183c (patch)
treea00b629d54bbdb70455d493b01db9abbb45f7873 /src/arch/arm/insts
parent564cc801c617bbe14d8bcb8d5e657e67aa26d7f4 (diff)
downloadgem5-ecf774bc561f139a13539d40dde075710f89183c.tar.xz
arm: Correctly display disassembly of vldmia/vstmia
The MicroMemOp class generates the disassembly for both integer and floating point instructions, but it would always print its first operand as an integer register without considering that the op may be a floating instruction in which case a float register should be displayed instead.
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/macromem.cc5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 42cb98a7c..cd77d6d5f 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -1483,7 +1483,10 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, ura);
+ if (isFloating())
+ printReg(ss, ura + FP_Reg_Base);
+ else
+ printReg(ss, ura);
ss << ", [";
printReg(ss, urb);
ss << ", ";