arch-arm: Rewrite MSR immediate instruction class

MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:

* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).

This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)

Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2 files changed, 48 insertions, 1 deletions

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 423aaca25..cf625ebef 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -35,6 +35,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Gabe Black
+ *          Giacomo Travaglini
  */
 
 #include "arch/arm/insts/misc64.hh"
@@ -321,6 +322,27 @@ MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
     return trap_to_mon;
 }
 
+RegVal
+MiscRegImmOp64::miscRegImm() const
+{
+    if (dest == MISCREG_SPSEL) {
+        return imm & 0x1;
+    } else {
+        panic("Not a valid PSTATE field register\n");
+    }
+}
+
+std::string
+MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printMiscReg(ss, dest);
+    ss << ", ";
+    ccprintf(ss, "#0x%x", imm);
+    return ss.str();
+}
+
 std::string
 MiscRegRegImmOp64::generateDisassembly(
     Addr pc, const SymbolTable *symtab) const
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index f70344bcb..741b7b5e0 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013,2017-2018 ARM Limited
+ * Copyright (c) 2011-2013,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -35,6 +35,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Gabe Black
+ *          Giacomo Travaglini
  */
 
 #ifndef __ARCH_ARM_INSTS_MISC64_HH__
@@ -142,6 +143,30 @@ class MiscRegOp64 : public ArmStaticInst
 
 };
 
+class MiscRegImmOp64 : public MiscRegOp64
+{
+  protected:
+    MiscRegIndex dest;
+    uint32_t imm;
+
+    MiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+                   OpClass __opClass, MiscRegIndex _dest,
+                   uint32_t _imm) :
+        MiscRegOp64(mnem, _machInst, __opClass, false),
+        dest(_dest), imm(_imm)
+    {}
+
+    /** Returns the "register view" of the immediate field.
+     * as if it was a MSR PSTATE REG instruction.
+     * This means basically shifting and masking depending on
+     * which PSTATE field is being set/cleared.
+     */
+    RegVal miscRegImm() const;
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+};
+
 class MiscRegRegImmOp64 : public MiscRegOp64
 {
   protected: