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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
| commit | 04ca96427c1c910f0bddb2403dec9ea517f3869b (patch) | |
| tree | 9543fed87f3a76b07a7074ab9408a2823f97873c /src/arch/arm/insts | |
| parent | 17aa2b0f1be705b0f33ff486509b6962cf1a541d (diff) | |
| download | gem5-04ca96427c1c910f0bddb2403dec9ea517f3869b.tar.xz | |
ARM: Predict target of more instructions that modify PC.
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/macromem.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index e1b754204..d05ac7728 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -113,6 +113,14 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, } else { *++uop = new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr); + if (reg == INTREG_PC) { + (*uop)->setFlag(StaticInst::IsControl); + if (!(condCode == COND_AL || condCode == COND_UC)) + (*uop)->setFlag(StaticInst::IsCondControl); + else + (*uop)->setFlag(StaticInst::IsUncondControl); + (*uop)->setFlag(StaticInst::IsIndirectControl); + } } } } else { |