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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-04-29 16:05:02 -0500
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-04-29 16:05:02 -0500
commit4a3f11149d791284a012af71067f6b2199aa165c (patch)
treec960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/arch/arm/insts
parent035a82ee2c7e9ee72163a6559f721b242427906d (diff)
downloadgem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file.
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/static_inst.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 260c29a84..9f878ac4d 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2014 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -335,7 +335,8 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
break;
case CCRegClass:
- panic("printReg: CCRegClass but ARM has no CC regs\n");
+ ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
+ break;
}
}