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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-07 17:17:16 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-22 10:52:55 +0000 |
| commit | fc278fffb78512ff3d62a906804d6b285edd00c7 (patch) | |
| tree | 5c8f488763041f6774ebada7609b86d6a3a865bd /src/arch/arm/insts | |
| parent | 3ed0c3c0bef2eefddcf2033e6ab9d22cf45c486d (diff) | |
| download | gem5-fc278fffb78512ff3d62a906804d6b285edd00c7.tar.xz | |
arch-arm: BadMode checking if corresponding EL is implemented
The old utility function called badMode was only checking if the mode
passed as an argument was a recognized mode. It was not checking if the
corresponding mode/EL was implemented. That function has been renamed to
unknownMode and a new badMode has been introduced. This is used by the
cpsrWriteByInstruction function. In this way any try to change the
execution mode won't succeed if the mode hasn't been implemented.
Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11196
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/static_inst.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/insts/static_inst.hh | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 40a1fe4b3..b7f235e98 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -961,7 +961,7 @@ static bool illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr) { const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode; - if (badMode(mode)) + if (unknownMode(mode)) return true; const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode; @@ -1000,7 +1000,7 @@ illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr) return true; } else { // aarch32 - return badMode32(mode); + return unknownMode32(mode); } return false; @@ -1029,7 +1029,7 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const } } else { new_cpsr.il = spsr.il; - if (spsr.width && badMode32((OperatingMode)(uint8_t)spsr.mode)) { + if (spsr.width && unknownMode32((OperatingMode)(uint8_t)spsr.mode)) { new_cpsr.il = 1; } else if (spsr.width) { new_cpsr.mode = spsr.mode; diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 69ae58e66..873dfff02 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -230,7 +230,7 @@ class ArmStaticInst : public StaticInst // Now check the new mode is allowed OperatingMode newMode = (OperatingMode) (val & mask(5)); OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode; - if (!badMode(newMode)) { + if (!badMode(tc, newMode)) { bool validModeChange = true; // Check for attempts to enter modes only permitted in // Secure state from Non-secure state. These are Monitor |