diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-10 15:35:26 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-21 14:25:56 +0000 |
| commit | 2a2c66c16c659af4c3588b6c1646d55c66ad53fe (patch) | |
| tree | 633dd84e28b040febbe2fd2efc7cd0a62dc7f60d /src/arch/arm/insts | |
| parent | d3ec34201c14d551e864372a89ccddb1c255e77a (diff) | |
| download | gem5-2a2c66c16c659af4c3588b6c1646d55c66ad53fe.tar.xz | |
arch-arm: Fix MSR/MRS disassemble
This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name
Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 28 | ||||
| -rw-r--r-- | src/arch/arm/insts/misc64.hh | 36 |
2 files changed, 61 insertions, 3 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 465bafa9e..b40de0229 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 ARM Limited + * Copyright (c) 2011-2013,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -53,7 +53,7 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string RegRegRegImmOp64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -71,3 +71,27 @@ UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", machInst); } + +std::string +MiscRegRegImmOp64::generateDisassembly( + Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printMiscReg(ss, dest); + ss << ", "; + printIntReg(ss, op1); + return ss.str(); +} + +std::string +RegMiscRegImmOp64::generateDisassembly( + Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printIntReg(ss, dest); + ss << ", "; + printMiscReg(ss, op1); + return ss.str(); +} diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index 5a0e18224..384d94628 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 ARM Limited + * Copyright (c) 2011-2013,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -89,4 +89,38 @@ class UnknownOp64 : public ArmStaticInst std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class MiscRegRegImmOp64 : public ArmStaticInst +{ + protected: + MiscRegIndex dest; + IntRegIndex op1; + uint32_t imm; + + MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, MiscRegIndex _dest, + IntRegIndex _op1, uint32_t _imm) : + ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), imm(_imm) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +class RegMiscRegImmOp64 : public ArmStaticInst +{ + protected: + IntRegIndex dest; + MiscRegIndex op1; + uint32_t imm; + + RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, + MiscRegIndex _op1, uint32_t _imm) : + ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), imm(_imm) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + #endif |