diff options
| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-10-13 19:22:10 +0100 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-10-13 19:22:10 +0100 |
| commit | bd0c2d5b0bf512aa5c172fe5676e151913e5e97d (patch) | |
| tree | 3aa61e0e7070664b605c216dff51f8d4d6847d8f /src/arch/arm/insts | |
| parent | 68fdccb30bd85cd99823fb411ec7ae67112062d7 (diff) | |
| download | gem5-bd0c2d5b0bf512aa5c172fe5676e151913e5e97d.tar.xz | |
isa,arm: Add missing AArch32 FP instructions
This commit adds missing non-predicated, scalar floating point
instructions. Specifically VRINT* floating point integer rounding
instructions and VSEL* floating point conditional selects.
Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/vfp.cc | 15 | ||||
| -rw-r--r-- | src/arch/arm/insts/vfp.hh | 21 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc index 03fdc83fa..c76f97ca6 100644 --- a/src/arch/arm/insts/vfp.cc +++ b/src/arch/arm/insts/vfp.cc @@ -123,6 +123,21 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) + const +{ + std::stringstream ss; + printMnemonic(ss); + printCondition(ss, cond); + printReg(ss, dest + FP_Reg_Base); + ss << ", "; + printReg(ss, op1 + FP_Reg_Base); + ss << ", "; + printReg(ss, op2 + FP_Reg_Base); + return ss.str(); +} + +std::string FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh index f28ab9e1f..de0c62161 100644 --- a/src/arch/arm/insts/vfp.hh +++ b/src/arch/arm/insts/vfp.hh @@ -979,6 +979,27 @@ class FpRegRegRegOp : public FpOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class FpRegRegRegCondOp : public FpOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + IntRegIndex op2; + ConditionCode cond; + + FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, ConditionCode _cond, + VfpMicroMode mode = VfpNotAMicroop) : + FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2), + cond(_cond) + { + setVfpMicroFlags(mode, flags); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class FpRegRegRegRegOp : public FpOp { protected: |