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| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:00 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 00da08902918da13fccc3f2266b7b2f5d0080708 (patch) | |
| tree | b495a0ceba7e073adca005cf84a7575d0aad5f27 /src/arch/arm/insts | |
| parent | 0747a432d25ade2c197ca6393270e12606419872 (diff) | |
| download | gem5-00da08902918da13fccc3f2266b7b2f5d0080708.tar.xz | |
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/static_inst.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/insts/static_inst.hh | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 99d1b817d..8501715d5 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -331,6 +331,12 @@ ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const } void +ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx) const +{ + ccprintf(os, "v%d", reg_idx); +} + +void ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const { ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]); diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 19af99a0f..486d30fe4 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -157,6 +157,7 @@ class ArmStaticInst : public StaticInst /// dependence tag number (FP or int). void printIntReg(std::ostream &os, RegIndex reg_idx) const; void printFloatReg(std::ostream &os, RegIndex reg_idx) const; + void printVecReg(std::ostream &os, RegIndex reg_idx) const; void printCCReg(std::ostream &os, RegIndex reg_idx) const; void printMiscReg(std::ostream &os, RegIndex reg_idx) const; void printMnemonic(std::ostream &os, |