ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.

3 files changed, 36 insertions, 2 deletions

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 2a45cf2e6..c03b7ccc1 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -896,6 +896,15 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 }
 
 std::string
+MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    ss << "[PC,CPSR]";
+    return ss.str();
+}
+
+std::string
 MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 1a2db8b9a..4933a1e7c 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp
     {
     }
 };
+
+/**
+ * Microops of the form
+ * PC   = IntRegA
+ * CPSR = IntRegB
+ */
+class MicroSetPCCPSR : public MicroOp
+{
+    protected:
+    IntRegIndex ura, urb, urc;
+
+    MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+                   IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
+        : MicroOp(mnem, machInst, __opClass),
+          ura(_ura), urb(_urb), urc(_urc)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 /**
  * Microops of the form IntRegA = IntRegB
  */
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index a4fc62603..324d86fed 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -97,14 +97,18 @@ class RfeOp : public MightBeMicro
     IntRegIndex base;
     AddrMode mode;
     bool wb;
-    static const unsigned numMicroops = 2;
+    IntRegIndex ura, urb, urc;
+    static const unsigned numMicroops = 3;
 
     StaticInstPtr *uops;
 
     RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
           IntRegIndex _base, AddrMode _mode, bool _wb)
         : MightBeMicro(mnem, _machInst, __opClass),
-          base(_base), mode(_mode), wb(_wb), uops(NULL)
+          base(_base), mode(_mode), wb(_wb),
+          ura(INTREG_UREG0), urb(INTREG_UREG1),
+          urc(INTREG_UREG2),
+          uops(NULL)
     {}
 
     virtual