arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

11 files changed, 195 insertions, 192 deletions

diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index 49ba3402a..d0a4f2924 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -95,7 +95,7 @@ BranchReg64::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -106,7 +106,7 @@ BranchRet64::generateDisassembly(
     std::stringstream ss;
     printMnemonic(ss, "", false);
     if (op1 != INTREG_X30)
-        printReg(ss, op1);
+        printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -125,7 +125,7 @@ BranchImmReg64::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
     printTarget(ss, pc + imm, symtab);
     return ss.str();
@@ -137,7 +137,7 @@ BranchImmImmReg64::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%#x, ", imm1);
     printTarget(ss, pc + imm2, symtab);
     return ss.str();
diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc
index f65219870..2f4dc117b 100644
--- a/src/arch/arm/insts/data64.cc
+++ b/src/arch/arm/insts/data64.cc
@@ -56,7 +56,7 @@ DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -84,9 +84,9 @@ DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -95,9 +95,9 @@ DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -107,9 +107,9 @@ DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -119,11 +119,11 @@ DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     return ss.str();
 }
 
@@ -132,11 +132,11 @@ DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -146,13 +146,13 @@ DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", ");
-    printReg(ss, op3);
+    printIntReg(ss, op3);
     return ss.str();
 }
 
@@ -162,7 +162,7 @@ DataXCondCompImmOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d, #%d", imm, defCc);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
@@ -175,9 +175,9 @@ DataXCondCompRegOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", defCc);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
@@ -190,11 +190,11 @@ DataXCondSelOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
     return ss.str();
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 9a3e70616..591f9fd79 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -1525,9 +1525,9 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    printIntReg(ss, ura);
     ss << ", ";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     ss << ", ";
     ccprintf(ss, "#%d", imm);
     return ss.str();
@@ -1538,9 +1538,9 @@ MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    printIntReg(ss, ura);
     ss << ", ";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     ss << ", ";
     ccprintf(ss, "#%d", imm);
     return ss.str();
@@ -1560,9 +1560,9 @@ MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    printIntReg(ss, ura);
     ccprintf(ss, ", ");
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     printExtendOperand(false, ss, (IntRegIndex)urc, type, shiftAmt);
     return ss.str();
 }
@@ -1572,9 +1572,9 @@ MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    printIntReg(ss, ura);
     ss << ", ";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     return ss.str();
 }
 
@@ -1583,11 +1583,11 @@ MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    printIntReg(ss, ura);
     ss << ", ";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     ss << ", ";
-    printReg(ss, urc);
+    printIntReg(ss, urc);
     return ss.str();
 }
 
@@ -1597,11 +1597,11 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     std::stringstream ss;
     printMnemonic(ss);
     if (isFloating())
-        printReg(ss, ura + FP_Reg_Base);
+        printFloatReg(ss, ura);
     else
-        printReg(ss, ura);
+        printIntReg(ss, ura);
     ss << ", [";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     ss << ", ";
     ccprintf(ss, "#%d", imm);
     ss << "]";
@@ -1613,11 +1613,11 @@ MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ",";
-    printReg(ss, dest2);
+    printIntReg(ss, dest2);
     ss << ", [";
-    printReg(ss, urb);
+    printIntReg(ss, urb);
     ss << ", ";
     ccprintf(ss, "#%d", imm);
     ss << "]";
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 558235340..3b57aae64 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -54,7 +54,7 @@ MemoryReg::printOffset(std::ostream &os) const
 {
     if (!add)
         os << "-";
-    printReg(os, index);
+    printIntReg(os, index);
     if (shiftType != LSL || shiftAmt != 0) {
         switch (shiftType) {
           case LSL:
@@ -82,11 +82,11 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", [";
-    printReg(ss, base);
+    printIntReg(ss, base);
     ss << "]";
     return ss.str();
 }
@@ -109,7 +109,7 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         printMnemonic(ss, "ib");
         break;
     }
-    printReg(ss, base);
+    printIntReg(ss, base);
     if (wb) {
         ss << "!";
     }
@@ -134,7 +134,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         printMnemonic(ss, "ib");
         break;
     }
-    printReg(ss, INTREG_SP);
+    printIntReg(ss, INTREG_SP);
     if (wb) {
         ss << "!";
     }
@@ -180,7 +180,7 @@ Memory::printInst(std::ostream &os, AddrMode addrMode) const
     printMnemonic(os);
     printDest(os);
     os << ", [";
-    printReg(os, base);
+    printIntReg(os, base);
     if (addrMode != AddrMd_PostIndex) {
         os << ", ";
         printOffset(os);
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index 324d86fed..ddd196676 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -211,7 +211,7 @@ class Memory : public MightBeMicro
     virtual void
     printDest(std::ostream &os) const
     {
-        printReg(os, dest);
+        printIntReg(os, dest);
     }
 
     void printInst(std::ostream &os, AddrMode addrMode) const;
@@ -253,7 +253,7 @@ class MemoryExImm : public MemoryImm
     void
     printDest(std::ostream &os) const
     {
-        printReg(os, result);
+        printIntReg(os, result);
         os << ", ";
         MemoryImm::printDest(os);
     }
@@ -277,7 +277,7 @@ class MemoryDImm : public MemoryImm
     {
         MemoryImm::printDest(os);
         os << ", ";
-        printReg(os, dest2);
+        printIntReg(os, dest2);
     }
 };
 
@@ -296,7 +296,7 @@ class MemoryExDImm : public MemoryDImm
     void
     printDest(std::ostream &os) const
     {
-        printReg(os, result);
+        printIntReg(os, result);
         os << ", ";
         MemoryDImm::printDest(os);
     }
@@ -341,7 +341,7 @@ class MemoryDReg : public MemoryReg
     {
         MemoryReg::printDest(os);
         os << ", ";
-        printReg(os, dest2);
+        printIntReg(os, dest2);
     }
 };
 
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 52e2fc7db..0aee63f2c 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -54,7 +54,7 @@ SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     std::stringstream ss;
     printMnemonic(ss, "", false);
     ccprintf(ss, ", [");
-    printReg(ss, base);
+    printIntReg(ss, base);
     ccprintf(ss, "]");
     return ss.str();
 }
@@ -65,9 +65,9 @@ void
 Memory64::startDisassembly(std::ostream &os) const
 {
     printMnemonic(os, "", false);
-    printReg(os, dest);
+    printIntReg(os, dest);
     ccprintf(os, ", [");
-    printReg(os, base);
+    printIntReg(os, base);
 }
 
 void
@@ -100,11 +100,11 @@ MemoryDImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, dest2);
+    printIntReg(ss, dest2);
     ccprintf(ss, ", [");
-    printReg(ss, base);
+    printIntReg(ss, base);
     if (imm)
         ccprintf(ss, ", #%d", imm);
     ccprintf(ss, "]");
@@ -116,13 +116,13 @@ MemoryDImmEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, result);
+    printIntReg(ss, result);
     ccprintf(ss, ", ");
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, dest2);
+    printIntReg(ss, dest2);
     ccprintf(ss, ", [");
-    printReg(ss, base);
+    printIntReg(ss, base);
     if (imm)
         ccprintf(ss, ", #%d", imm);
     ccprintf(ss, "]");
@@ -173,11 +173,11 @@ MemoryEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, result);
+    printIntReg(ss, result);
     ccprintf(ss, ", [");
-    printReg(ss, base);
+    printIntReg(ss, base);
     ccprintf(ss, "]");
     return ss.str();
 }
@@ -187,7 +187,7 @@ MemoryLiteral64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d", pc + imm);
     return ss.str();
 }
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 790989d9d..0114a4aba 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -47,21 +47,20 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
     bool foundPsr = false;
     for (unsigned i = 0; i < numSrcRegs(); i++) {
-        RegIndex idx = srcRegIdx(i);
-        RegIndex rel_idx;
-        if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
+        RegId reg = srcRegIdx(i);
+        if (reg.regClass != MiscRegClass) {
             continue;
         }
-        if (rel_idx == MISCREG_CPSR) {
+        if (reg.regIdx == MISCREG_CPSR) {
             ss << "cpsr";
             foundPsr = true;
             break;
         }
-        if (rel_idx == MISCREG_SPSR) {
+        if (reg.regIdx == MISCREG_SPSR) {
             ss << "spsr";
             foundPsr = true;
             break;
@@ -80,17 +79,16 @@ MsrBase::printMsrBase(std::ostream &os) const
     bool apsr = false;
     bool foundPsr = false;
     for (unsigned i = 0; i < numDestRegs(); i++) {
-        int idx = destRegIdx(i);
-        if (idx < Misc_Reg_Base) {
+        RegId reg = destRegIdx(i);
+        if (reg.regClass != MiscRegClass) {
             continue;
         }
-        idx -= Misc_Reg_Base;
-        if (idx == MISCREG_CPSR) {
+        if (reg.regIdx == MISCREG_CPSR) {
             os << "cpsr_";
             foundPsr = true;
             break;
         }
-        if (idx == MISCREG_SPSR) {
+        if (reg.regIdx == MISCREG_SPSR) {
             if (bits(byteMask, 1, 0)) {
                 os << "spsr_";
             } else {
@@ -142,7 +140,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     std::stringstream ss;
     printMsrBase(ss);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -151,11 +149,11 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, dest2);
+    printIntReg(ss, dest2);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -164,11 +162,11 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     return ss.str();
 }
 
@@ -186,7 +184,7 @@ RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -196,9 +194,9 @@ RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -207,11 +205,11 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -221,13 +219,13 @@ RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ss << ", ";
-    printReg(ss, op3);
+    printIntReg(ss, op3);
     return ss.str();
 }
 
@@ -236,11 +234,11 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     return ss.str();
 }
 
@@ -249,9 +247,9 @@ RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -261,9 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -273,9 +271,9 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -285,7 +283,7 @@ RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -295,9 +293,9 @@ RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -307,9 +305,9 @@ RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, ", imm);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
@@ -318,10 +316,10 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", #%d, ", imm);
     printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     return ss.str();
 }
 
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 3553020da..465bafa9e 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -44,9 +44,9 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", #%d, #%d", imm1, imm2);
     return ss.str();
 }
@@ -57,11 +57,11 @@ RegRegRegImmOp64::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index df27ed822..99d1b817d 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -291,57 +291,59 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
     return 0;
 }
 
-
 void
-ArmStaticInst::printReg(std::ostream &os, int reg) const
+ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
 {
-    RegIndex rel_reg;
-
-    switch (regIdxToClass(reg, &rel_reg)) {
-      case IntRegClass:
-        if (aarch64) {
-            if (reg == INTREG_UREG0)
-                ccprintf(os, "ureg0");
-            else if (reg == INTREG_SPX)
-               ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
-            else if (reg == INTREG_X31)
-                ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
-            else
-                ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg);
-        } else {
-            switch (rel_reg) {
-              case PCReg:
-                ccprintf(os, "pc");
-                break;
-              case StackPointerReg:
-                ccprintf(os, "sp");
-                break;
-              case FramePointerReg:
-                ccprintf(os, "fp");
-                break;
-              case ReturnAddressReg:
-                ccprintf(os, "lr");
-                break;
-              default:
-                ccprintf(os, "r%d", reg);
-                break;
-            }
+    if (aarch64) {
+        if (reg_idx == INTREG_UREG0)
+            ccprintf(os, "ureg0");
+        else if (reg_idx == INTREG_SPX)
+            ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
+        else if (reg_idx == INTREG_X31)
+            ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
+        else
+            ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
+    } else {
+        switch (reg_idx) {
+          case PCReg:
+            ccprintf(os, "pc");
+            break;
+          case StackPointerReg:
+            ccprintf(os, "sp");
+            break;
+          case FramePointerReg:
+             ccprintf(os, "fp");
+             break;
+          case ReturnAddressReg:
+             ccprintf(os, "lr");
+             break;
+          default:
+             ccprintf(os, "r%d", reg_idx);
+             break;
         }
-        break;
-      case FloatRegClass:
-        ccprintf(os, "f%d", rel_reg);
-        break;
-      case MiscRegClass:
-        assert(rel_reg < NUM_MISCREGS);
-        ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
-        break;
-      case CCRegClass:
-        ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
-        break;
     }
 }
 
 void
+ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
+{
+    ccprintf(os, "f%d", reg_idx);
+}
+
+void
+ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
+{
+    ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
+}
+
+void
+ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
+{
+    assert(reg_idx < NUM_MISCREGS);
+    ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
+}
+
+void
 ArmStaticInst::printMnemonic(std::ostream &os,
                              const std::string &suffix,
                              bool withPred,
@@ -471,7 +473,7 @@ ArmStaticInst::printShiftOperand(std::ostream &os,
     bool firstOp = false;
 
     if (rm != INTREG_ZERO) {
-        printReg(os, rm);
+        printIntReg(os, rm);
     }
 
     bool done = false;
@@ -520,7 +522,7 @@ ArmStaticInst::printShiftOperand(std::ostream &os,
         if (immShift)
             os << "#" << shiftAmt;
         else
-            printReg(os, rs);
+            printIntReg(os, rs);
     }
 }
 
@@ -531,7 +533,7 @@ ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
 {
     if (!firstOperand)
         ccprintf(os, ", ");
-    printReg(os, rm);
+    printIntReg(os, rm);
     if (type == UXTX && shiftAmt == 0)
         return;
     switch (type) {
@@ -568,7 +570,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
     // Destination
     if (rd != INTREG_ZERO) {
         firstOp = false;
-        printReg(os, rd);
+        printIntReg(os, rd);
     }
 
     // Source 1.
@@ -576,7 +578,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
         if (!firstOp)
             os << ", ";
         firstOp = false;
-        printReg(os, rn);
+        printIntReg(os, rn);
     }
 
     if (!firstOp)
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 55d16f69d..19af99a0f 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -155,7 +155,10 @@ class ArmStaticInst : public StaticInst
 
     /// Print a register name for disassembly given the unique
     /// dependence tag number (FP or int).
-    void printReg(std::ostream &os, int reg) const;
+    void printIntReg(std::ostream &os, RegIndex reg_idx) const;
+    void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
+    void printCCReg(std::ostream &os, RegIndex reg_idx) const;
+    void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
     void printMnemonic(std::ostream &os,
                        const std::string &suffix = "",
                        bool withPred = true,
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index c76f97ca6..f72fba675 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -51,9 +51,9 @@ FpCondCompRegOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", #%d", defCc);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
@@ -66,11 +66,11 @@ FpCondSelOp::generateDisassembly(
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    printReg(ss, dest);
+    printIntReg(ss, dest);
     ccprintf(ss, ", ");
-    printReg(ss, op1);
+    printIntReg(ss, op1);
     ccprintf(ss, ", ");
-    printReg(ss, op2);
+    printIntReg(ss, op2);
     ccprintf(ss, ", ");
     printCondition(ss, condCode, true);
     return ss.str();
@@ -81,9 +81,9 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     return ss.str();
 }
 
@@ -92,7 +92,7 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -102,9 +102,9 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -114,11 +114,11 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     return ss.str();
 }
 
@@ -129,11 +129,11 @@ FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
     std::stringstream ss;
     printMnemonic(ss);
     printCondition(ss, cond);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     return ss.str();
 }
 
@@ -142,13 +142,13 @@ FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     ss << ", ";
-    printReg(ss, op3 + FP_Reg_Base);
+    printFloatReg(ss, op3);
     return ss.str();
 }
 
@@ -157,11 +157,11 @@ FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Reg_Base);
+    printFloatReg(ss, dest);
     ss << ", ";
-    printReg(ss, op1 + FP_Reg_Base);
+    printFloatReg(ss, op1);
     ss << ", ";
-    printReg(ss, op2 + FP_Reg_Base);
+    printFloatReg(ss, op2);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }